Signed

Signed vs. Unsigned in VHDL

All Digital Designers must understand how math works inside of an FPGA or ASIC. The first step to that is understanding how signed and unsigned signal types work. Signed and unsigned types exist in the numeric_std package, which is part of the ieee library. It should be noted that there is another packet file that is used frequently to perform mathematical operations: std_logic_arith. Nevertheless, std_logic_arith is not an official ieee supported package file and information technology is non recommended for utilize in digital designs.

A signal that is defined as type signed means that the tools interpret this signal to be either positive or negative. A signal that is divers equally type unsigned ways that the point will be just positive. Internally, the FPGA will use Two's Complement representation. For example, a iii-chip point tin can be interpreted according to the tabular array beneath:

Bits	Unsigned Value	Signed Value
011	iii	3
010	2	2
001	i	ane
000	0	0
111	7	-1
110	6	-2
101	five	-3
100	4	-4

Are y'all confused yet? You should be, this is not intuitive! Let'southward look at an case which volition hopefully clear things up. The file beneath tests out how signed unsigned works. What needs to be understood is that whether or not the signals are divers every bit signed or unsigned does not impact how the bodily binary math is performed.

For instance: For two signed vectors 10001 + 00010 the answer is nevertheless 10011, But it'south the estimation of the result that is unlike.
For the unsigned instance, the answer (10011) represents 19.
For the signed instance, the answer (10011) represents -thirteen.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity signed_unsigned is   port (     i_rst_l : in std_logic;     i_clk   : in std_logic;     i_a     : in std_logic_vector(four downto 0);     i_b     : in std_logic_vector(4 downto 0)     ); finish signed_unsigned;  architecture behave of signed_unsigned is   bespeak rs_SUM_RESULT : signed(4 downto 0)   := (others => '0');   signal ru_SUM_RESULT : unsigned(4 downto 0) := (others => '0');   bespeak rs_SUB_RESULT : signed(iv downto 0)   := (others => '0');   bespeak ru_SUB_RESULT : unsigned(four downto 0) := (others => '0');          begin    -- Purpose: Add ii numbers.  Does both the signed and unsigned   -- addition for demonstration.  This process is synthesizable.   p_SUM : process (i_clk, i_rst_l)   begin      if i_rst_l = '0' then             -- asynchronous reset (agile low)       rs_SUM_RESULT <= (others => '0');       ru_SUM_RESULT <= (others => '0');     elsif rising_edge(i_clk) then              ru_SUM_RESULT <= unsigned(i_a) + unsigned(i_b);       rs_SUM_RESULT <= signed(i_a) + signed(i_b);          end if;          end process p_SUM;       -- Purpose: Subtract two numbers.  Does both the signed and unsigned   -- subtraction for sit-in.  This procedure is synthesizable.   p_SUB : process (i_clk, i_rst_l)   begin      if i_rst_l = '0' then             -- asynchronous reset (agile low)       rs_SUB_RESULT <= (others => '0');       ru_SUB_RESULT <= (others => '0');     elsif rising_edge(i_clk) and then                  ru_SUB_RESULT <= unsigned(i_a) - unsigned(i_b);       rs_SUB_RESULT <= signed(i_a) - signed(i_b);          finish if;          end process p_SUB;  stop behave;        

Testbench:

library ieee; use ieee.std_logic_1164.all;  entity example_signed_unsigned_tb is terminate example_signed_unsigned_tb;  architecture behave of example_signed_unsigned_tb is    --Registers   point r_CLK   : std_logic                    := '0';   indicate r_RST_L : std_logic                    := '0';   indicate r_A     : natural                      := 0;   point r_B     : natural                      := 0;   signal r_A_SLV : std_logic_vector(4 downto 0) := (others => '0');   signal r_B_SLV : std_logic_vector(4 downto 0) := (others => '0');    constant c_CLK_PERIOD : time := 10 ns;    component example_signed_unsigned is     port (       i_rst_l        : in  std_logic;       i_clk          : in  std_logic;       i_a            : in  std_logic_vector(4 downto 0);       i_b            : in  std_logic_vector(4 downto 0)       );   end component example_signed_unsigned;  begin      i_DUT: example_signed_unsigned     port map (      i_rst_l          => r_RST_L,      i_clk            => r_CLK,      i_a              => r_A_SLV,      i_b              => r_B_SLV      );       clk_gen : process is   begin     r_CLK <= '0' after c_CLK_PERIOD/ii, 'ane' after c_CLK_PERIOD;     wait for c_CLK_PERIOD;   end process clk_gen;     process   brainstorm          r_RST_L <= '0';     wait for 20 ns;     r_RST_L <= '1';     wait for 20 ns;      r_A_SLV <= "01001";     r_B_SLV <= "00110";        look for xx ns;      r_A_SLV <= "10001";     r_B_SLV <= "00110";     wait for 20 ns;      r_A_SLV <= "10001";     r_B_SLV <= "00001";     look for 20 ns;      r_A_SLV <= "10001";     r_B_SLV <= "00010";     wait for 20 ns;          r_A_SLV <= "11111";     r_B_SLV <= "00001";     await for 20 ns;      r_A_SLV <= "00000";     r_B_SLV <= "00001";     look for 20 ns;         expect;        finish process;  end bear;        

Modelsim simulation moving ridge output Values Shown in HEX

Modelsim simulation wave output Values Shown in DECIMAL

Compare the 2 modelsim screenshots above. In the get-go you can see that the results of the mathematical functions are exactly the same when represented in hex. It's the interpretation of the results that is different. This can be seen by looking at the lesser screenshot. When Modelsim displays the results in decimal it interprets some of them as negative numbers. When using signed and unsigned types you must be very careful! Hopefully yous empathize this topic a little better. I experience like this is an expanse that many digital designers struggle with, and then if there is something that you lot do not fully understand please send me an email via the Contact Link on the Sidebar and I will endeavour to brand it clearer.

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